This invention relates to the singularizing process of dies, more specifically, to parallel chip probe (CP) test products using a scribe line etch to singularize the dies.
Die sawing is used to singularize dies. However, die sawing becomes unfeasible for products with scribe lines of 60 microns or less. When an etching process is applied to the scribe lines for separating dies, the metal routing in the scribe lines requires expensive and complex photolithography and etching processes. Various problems associated with the scribe line etching process include seal ring damage, copper etching, and corrosion of the exposed copper. Therefore, what is needed is an integrated circuit (IC) structure and method to etch scribe lines addressing the above issues.